Static random access memory (SRAM) cells are commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. FIG. 1 illustrates an exemplary circuit diagram of a typical six-MOS transistor SRAM cell, which includes pass-gate transistors 10 and 24, pull-up transistors 12 and 16, and pull-down transistors 14 and 18. Gates 2 and 4 of the respective pass-gate transistors 10 and 24 are controlled by word-line WL that determines whether the current SRAM cell is selected or not. A latch formed of pull-up transistors 12 and 16 and pull-down transistors 14 and 18 stores a state. The stored state can be read through bit lines BL and BLB.
With the down-scaling of integrated circuits, the operation voltages of SRAM cells are lowered. This causes the reduction in the cell currents, and hence the reduction in the speed in the read operations. The reduction in the read speed may cause sense amplifiers to amplify wrong signals. Further, the lowered operation voltages cause the reduction in static noise margin, which in turn causes the reduction in the read and write margins of the SRAM cells. Reduced read and write margins may cause errors in the respective read and write operations. Conventionally, to improve the read and write margins, dynamic powers were provided. For example, the write margin can be improved by increasing bit-line voltage and/or reducing power supply voltage VDD during the write operations, while the read margin can be improved by reducing bit-line voltage and/or increasing power supply voltage VDD during the read operations. However, such a solution suffers from drawbacks. For example, complicated circuits have to be designed to provide the dynamic power. Additionally, it takes time for the dynamic power to be generated, and thus the read and write operations are slowed down.
Accordingly, new SRAM cells having improved read and write margins, while at the same time overcoming the deficiency of the prior art, are needed.